The semiconductor industry is continuously reducing the dimensions of the devices. In Back End Of Line (BEOL) processing it concerns the reducing dimensions of conductive layers as well as the separation of the different conductive structures to each other. Lowering the capacitance in between these structures becomes extremely important and low-k materials replace conventional dielectric insulating materials. The use of these (porous) low-k materials as dielectric materials in interconnect structures brings new issues to the semiconductor processing. Examples of these issues include photoresist poisoning and low-k damage due to etch, ash and/or clean processes.
Photoresist poisoning is a particular problem when 248 nm (DUV) or 193 nm (ArF) wavelength photoresists are used in conjunction with porous low-k materials. The presence of traces of base nitrogen containing compounds such as amines may neutralize the acids generated upon exposure of 248 nm or 193 nm photoresist and thus inhibiting the chemically amplified acid reaction what is referred to as photoresist poisoning. The altered photoresist material may not be lithographically patterned as expected and result in imprecisely formed features in the photoresist material or excessive photoresist residue remaining on the substrate surface after photoresist development, both of which can detrimentally affect subsequent processes, such as etching processes.
Amines, may originate directly from deposited materials adjacent to the resist layer. Amines can also contaminate indirectly the resist material, such as by diffusion through one or more layers, outgassing of materials during processing steps (such as annealing and plasma treatment) and by etching processes which may expose underlying nitrogen containing layers (such as silicon nitride etch stop layers) to any subsequently deposited resist materials.
Other materials that may also result in resist poisoning include base compounds containing hydroxyl groups.
With the via-first approach for dual damascene patterning, the use of photoresist layers on dielectric layers often results in “poisoning” of the line imaging resist which is done after vias are fully or partially etched into the dielectric.
The poisoning is probably due to absorption and/or generation and liberation of amine compounds from the insulator, as a result of its finite permeability and the use of N2 and H2 process gases in the films below, as well as in the etching and stripping of patterns prior to applying the photoresist where the poisoning is observed. The poisoning problem appears to be much worse when the dielectric layer is a porous low-k insulator applied using chemical vapor deposition (CVD), as compared to silicate glass dielectric layers. This is thought to be a result of the increased permeability of low-k insulators, the use of N2O as a carrier gas in some deposition recipes, and the common use of reducing chemistries such as N2 and H2 for stripping prior lithographic patterns.
Another important issue in integrating low-k dielectrics is the plasma damage caused by etching, stripping and post etch cleaning. The plasma species that are diffused into the low-k film may change the composition of the film and its structure. The use of oxygen containing etch/strip chemistries typically results in depletion of the carbon present in the film, making the film hydrophilic and susceptible to water (k value>>80) adsorption, which leads to an increase of the k-value of the film. This problem is becoming even more important with the miniaturization of ICs where the feature size becomes comparable to the damaged region.
Several approaches are described in the state of the art to solve the poisoning problems but these are incomplete and too complicated.
One attempt is to use a resist material that is less sensitive to poisoning. However, such resist materials compromise imaging resolution and decrease lithographic process window.
Another attempt is to modify the dielectric material so that it causes less poisoning. For example, in U.S. Pat. No. 6,147,009 to Grill et al., the use of N2O as an oxidizing carrier gas is avoided by using a siloxane-based precursor and He gas to make low-k SiCO(H) films, thereby eliminating a source of nitrogen in the as-deposited film. This may prevent poisoning of a first photoresist material on the blanket SiCO(H) film, but after the pattern is etched into the SiCO(H) film and the resist is stripped, amines may still be generated and may poison a subsequent photoresist patterning step such as would be required for dual damascene interconnects.
Another method is to eliminate poisoning of photoresist by pre-treating the low-k material with e.g. acidic compounds. In U.S. Publ. No. 2002/0081855-A1 an in-situ plasma treatment is disclosed which immediately removes the source of poisoning by reducing or eliminating poisoning at trench patterning level. However, such modifications may adversely affect the dielectric constant and other characteristics of the insulating materials.
Another approach with partial success is to deposit a barrier material after via etch. In this approach, the via is lined with a very thin layer of a barrier material such as TEOS or silane SiO2, thereby encapsulating the poisoning source. The liner material must have excellent conformality. Since it is difficult to deposit materials in high-aspect ratio vias, this approach may not be extendable to future technologies. Defects in thin regions of this liner may allow poisoning gases to pass through, and even with low statistical occurrence may cause an unacceptable level of defective patterns in the line imaging layer. An example of this approach is described in U.S. Pat. No. 6,645,864.
In U.S. Pat. No. 6,713,386 to Hu et al. the low-k material is exposed after via etch to a plasma containing gas components such as oxygen, carbon dioxide, ozone or hydrogen peroxide such that a protective layer is formed on the surface of the low-k material which neutralizes nitrogen. This is however not without the risk of damaging the low-k material and increasing the k-value of the bulk low-k material.
Another approach for preventing resist poisoning during patterning is described in US Publ. No. 2004/127016-A1. The use of a dual cap layer is disclosed. The dual cap layer is formed over the low-k insulator layer prior to the etching of a via or trench toward an underlying conductor. The dual cap layer includes a layer of silicon carbide and a layer of silicon nitride. The silicon carbide layer maintains the critical dimension of the via or trench as it is etched through the insulating layer, while the silicon nitride layer inhibits the failure mechanism of resist poisoning. This approach is only valid for single damascene processing and not applicable for etching a trench over a patterned via structure with the via-first approach in dual damascene processing.
US Publ. No. 2004/0087164-A1 to Bao et al. discloses the use of an I-line or deep UV photoresist as barrier layer for use in the via-first approach for dual damascene patterning. The barrier layer is deposited on the low-k material after via etching. The resist used as barrier layer comprises hydroxy groups that can attract nitrogen containing compounds. Prior to the deposition of the barrier layer an inert polymeric resin can be deposited in the via to close the via or optionally the spin-coated barrier layer can be used to fill the via and form a coplanar layer on the damascene stack. A trench is etched within the via structure with an oxide etchant (plasma) which consumes the photoresist and BARC layers and consumes a portion of the barrier layer and resin layer. In the case of CVD low-k materials, this oxidizing plasma will cause low-k damage to the sidewalls of the trenches. After trench etching there is still a considerable amount of barrier layer and resin layer that needs to be removed by means of a wet stripping process (oxidizing solution containing H2SO4/H2O2) which involves a further risk of low-k damage.
US Publ. No. 2004/0266201-A1 by Wille et al. discloses an alternative method making use of a barrier layer for use in the via-first approach for dual damascene patterning. A barrier layer is deposited on the upper surface of the low-k material after via etching. A planarizing material is also here deposited to fill the via prior to the barrier layer deposition. The trench etching in the low-k material is performed by means of an O2 comprising plasma which introduces low-k damage if the low-k material is a SiCO(H) material (also called CVD low-k material). The barrier layer is removed during the trench etching. The remaining part of the planarizing material in the bottom part of the via still needs to be removed (strip) by means of an O2 comprising strip chemistry which introduces again damage to the sidewalls of the trenches.
Thus, the prior art proposes several solutions for eliminating resist poisoning but all of them do have serious drawbacks and shortcomings. The prior art does never provide a solution that simultaneously solves the problem of eliminating photoresist poisoning and avoiding or at least minimizing plasma damage of the dielectric material. On the contrary, some of the prior art solutions to avoid photoresist poisoning create low-k damage.